Data pattern analysis using optimized deterministic finite &amp;#8206;automation

ABSTRACT

Techniques for data pattern analysis using deterministic finite automaton are described herein. In one embodiment, a number of transitions from a current node to one or more subsequent nodes representing one or more sequences of data patterns is determined, where each of the current node and subsequent nodes is associated with a deterministic finite automaton (DFA) state. A data structure is dynamically allocated for each of the subsequent nodes for storing information associated with each of the subsequent nodes, where data structures for the subsequent nodes are allocated in an array maintained by a data structure corresponding to the current node if the number of transitions is greater than a predetermined threshold. Other methods and apparatuses are also described.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation and claims the prioritybenefit of U.S. patent application Ser. No. 13/196,484 filed Aug. 2,2011, which is a continuation and claims the priority benefit of U.S.patent application Ser. No. 11/778,546 filed Jul. 16, 2007, now U.S.Pat. No. 7,991,723, the disclosures of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to data pattern analysis. Moreparticularly, this invention relates to data pattern analysis usingdeterministic finite automaton.

2. Description of the Related Art

Deterministic finite automaton (DFA) or deterministic finite statemachine is a set of states tied together by a set of transitions, wheretransitions specify movement from one state to another based on someinput. Thus, a deterministic finite automaton at a given state and for agiven input has only one transition to a next state. Examples of suchdeterministic finite automaton may be designed in hardware or softwareto produce results based on the state and any input. Some applicationsfor deterministic finite automaton are used in electronic systems, suchas network equipment and computer operated systems, to control and runprocesses.

To increase the speed at which a deterministic finite automaton operateson an electronic system current systems load an array into memory foreach state of the deterministic finite automaton. Each array containsinformation on the current state and defines what the next state will begiven a certain input. As the number of states and transitions betweenstates of a deterministic finite automaton increases the size of thearray also increases. This creates the need for large amounts of memorynecessary to store the information needed to execute a deterministicfinite automaton. As the memory demands increase so does the cost ofimplementing a deterministic finite automaton.

SUMMARY OF THE PRESENTLY CLAIMED INVENTION

Techniques for data pattern analysis using deterministic finiteautomaton are described herein. In one embodiment, a number oftransitions from a current node to one or more subsequent nodesrepresenting one or more sequences of data patterns is determined, whereeach of the current node and subsequent nodes is associated with adeterministic finite automaton (DFA) state. A data structure isdynamically allocated for each of the subsequent nodes for storinginformation associated with each of the subsequent nodes, where datastructures for the subsequent nodes are allocated in an array maintainedby a data structure corresponding to the current node if the number oftransitions is greater than a predetermined threshold.

Other features of the present invention will be apparent from theaccompanying drawings and from the detailed description which follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings in which likereferences indicate similar elements.

FIG. 1 is a block diagram illustrating an example of a networkconfiguration according to one embodiment.

FIGS. 2A-2B are state diagrams illustrating an exemplary DFA accordingto certain embodiments of the invention.

FIG. 3 is a state diagram illustrating an example of DFA states whichmay represent a data pattern.

FIGS. 4A-4B are block diagrams illustrating examples of data structureconfigurations according to certain embodiments of the invention.

FIGS. 5A-5B are flow diagrams illustrating a process for data patternanalysis according to certain embodiments of the invention.

FIGS. 6A-6B are pseudo code representing examples of data structuresaccording to certain embodiments of the invention.

FIG. 7 is a diagram of a network of computer systems, which may be usedwith an embodiment of the invention.

FIG. 8 is a block diagram of a digital processing system which may beused with one embodiment of the invention.

DETAILED DESCRIPTION

Techniques for data pattern analysis using deterministic finiteautomaton are described herein. In the following description, numerousdetails are set forth to provide a more thorough explanation ofembodiments of the present invention. It will be apparent, however, toone skilled in the art, that embodiments of the present invention may bepracticed without these specific details. In other instances, well-knownstructures and devices are shown in block diagram form, rather than indetail, in order to avoid obscuring embodiments of the presentinvention.

Reference in the specification to “one embodiment” or “an embodiment”means that a particular feature, structure, or characteristic describedin connection with the embodiment is included in at least one embodimentof the invention. The appearances of the phrase “in one embodiment” invarious places in the specification do not necessarily all refer to thesame embodiment.

Recently, DFA states have been widely used in identifying certain datapatterns of data traffics such as, for example, antivirus, anti-spywareand/or content filtering processes in a network environment. Each DFAstate is associated with a data structure to store certain informationregarding to a respective DFA state such as target or matched data, linkreferences to other data structures of other DFA states. The datastructures of DFA states that represent certain data pattern may bereferenced one another. A first data structure may reference a seconddata structure either including the whole second data structure (e.g.,an array) or alternatively, a link referenced to an address of thesecond data structure (e.g., a linked-list structure). As describedabove, if the first data structure contains the entire second datastructure, processing logic can access from the first data structure tothe second data structure faster, but it requires more memory to retainthe second data structure. In a linked-list manner, it takes lessmemory; however, it accesses slower.

According to certain embodiments of the invention, dependent uponcertain data patterns being examined, data structures for the DFA statesmay be allocated in an array manner, a linked-list manner, or acombination of both, to optimize the memory usage (e.g., a hybridapproach). For example, given the fact that some states do notnecessarily have all 256 transitions (e.g., standard 256 ACSII codesrepresenting 256 characters) associated with them and some do, forcertain states with more than or equal to a certain threshold, most orall transitions are allocated as pointers in a dynamic array. For stateswhich have transitions fewer than certain threshold, the transitions maybe allocated in a linked-list manner in which each state requires onlytwo pointers, one referencing to its parent and the other onereferencing to its child. Alternatively, for a given state of a sequenceof state representing a data sequence, based on a relationship betweenthe given state and its top parent state (e.g., root state), a datastructure for the given state may be allocated in a data array or in alinked-list manner. For example, if a given node is within apredetermined distance from its root node, the data structurecorresponding to the given node may be allocated in an array; otherwise,the data structure may be allocated in a linked-list manner. Thedistance threshold may be user configurable and/or specified in the datastructure of the root node. Other configurations may exist.

FIG. 1 is a block diagram illustrating an example of a networkconfiguration according to one embodiment. Referring to FIG. 1, in oneembodiment, the network configuration 100 includes a network accessdevice 104 providing network access services for one or more networknodes 106-107 over a first network 105 which may be a local area network(LAN). In order to access remote nodes 101-102 (e.g., Web servers orpeer nodes) over a second network 103 (e.g., an external network), eachof the nodes 106-107 has to go through the network access device 104 andoptionally, a network service provider (e.g., an Internet serviceprovider or ISP) in order to access remote nodes 101-102.

In one embodiment, the connection between the network access device 104and the network 103 may be a wired connection. Alternatively, such aconnection may be a wireless connection; for example, a satellite or anIEEE 802.1x compatible connection. The network 103 may be a wide areanetwork (WAN), such as, for example, the Internet. The network 105 maybe a home network using an IEEE 802.1x compatible protocol.Alternatively, the network 105 may be a local network within anorganization (e.g., an Intranet). The network 105 may be a wired orwireless network, or a combination of both, using a variety of networkprotocols, such as, Ethernet and/or IEEE 802.1x compatible protocols,such as, for example, Wi-Fi and/or Bluetooth protocols. Wirelessconnections may include both RF and non-RF links, for example, an IRlink. Wired connections may include both electrical and non-electricallinks, for example, fiber optic links.

According to one embodiment, network access device 104 (e.g., gatewaydevice) includes packet inspection logic 108 which may be implemented aspart of an antivirus/spyware and/or content filtering function of thenetwork access device 104. Packet inspection logic 108 may inspectincoming and/or outgoing data packets to detect certain data patternswhich may be used to identify certain offensive data such as viruses orcertain offensive content. The packet inspection logic 108 may usemultiple DFA states to identify the data patterns, where each DFA isassociated with a data structure (e.g., DFA data structures 109) tostore certain state information of the respective DFA state. Accordingto one embodiment, the DFA data structures 109 may be allocateddependent upon the specific transitions from one DFA state to anotherDFA state of a data pattern. The data structures of the child nodes maybe allocated in a dynamic array fashion, a linked-list manner, or acombination of both. For example, for certain states with more than orequal to a certain threshold, most or all transitions are allocated aspointers in a dynamic array. For states which have transitions fewerthan certain threshold, the transitions may be allocated in alinked-list manner in which each state requires only two pointers, onereferencing to its parent and the other one referencing to its child.Furthermore, a data structure for a given node may be allocated in anarray or in a linked-list manner dependent upon its relationship (e.g.,distance from the root node) with respect to its top parent node or rootnode. As a result, memory usage for the DFA data structures may beoptimized without compromising the performance of content scanning.

FIG. 2A is a state diagram illustrating an exemplary DFA according toone embodiment of the invention. In this example, an IPS (intrusiondetection/prevention system) is programmed to detect and to prevent apattern of “0111” to pass through. The DFA 200 shown in FIG. 2Acorresponds to this pattern. Processing logic may use the DFA 200 toperform pattern matching on a number of packets to determine whether thepackets contain the pattern “0111”. Furthermore, to simplify theillustration, it is assumed in this example that each packet containsonly one digit. However, it should be appreciated that the concept isapplicable to scenarios where a packet contains more than one digitand/or alphabetic letters.

Referring to FIG. 2A, the DFA 200 includes 5 states 211-219. The states211-219 in the DFA 200 may be referred to as nodes. Pattern matchingbegins at the initial state 211. If a packet received contains a “1”,processing logic remains in the initial state 211. If the packetcontains a “0”, which corresponds to the first digit in thepredetermined pattern, processing logic transitions to the A state 213.If processing logic receives a “0” subsequently, processing logicremains in the A state 213. If processing logic receives a “1”, whichcorresponds to the second digit in the predetermined pattern, thenprocessing logic transitions into the B state 215. From the B state 215,processing logic may transition back to the A state 213 if the nextpacket received contains a “0”. If the next packet received contains a“1”, which corresponds to the third digit in the predetermined pattern,then processing logic transitions to the C state 217.

From the C state 217, processing logic may transition back to the Astate 213 if the next packet received contains a “0”. If the next packetreceived contains a “1”, which corresponds to the last digit in thepredetermined pattern, then processing logic transitions to the finalstate 219. When processing logic reaches the final state 219, processinglogic knows that the packets received so far contains the predeterminedpattern. Hence, processing logic may perform the appropriate operationsin response to receiving the predetermined pattern, such as block thepacket of the predetermined pattern last received and issuing an alarmto alert system administrators. To keep track of which state of the DFAprocessing logic is in, processing logic may use a logical pointer topoint to the current state of the DFA. For example, a logical pointer221 in FIG. 2A points at state B 215 to indicate that state B 215 is thecurrent state of the pattern matching.

One advantage of using the DFA to perform pattern matching on packets isto eliminate the need to reassemble the packets because processing logiccan walk through the DFA as each packet is received and examined. Ifprocessing logic reaches a final state, there is a match between thepattern contained in the packets received so far and the predeterminedpattern. As mentioned above, a pattern is typically broken up into anumber of segments and each segment is transmitted using a packet. Usingthe DFA, processing logic may not have to reassemble the packets inorder to find out what the pattern contained in the packets is in orderto match the pattern against a predetermined pattern. Processing logicmay perform pattern matching on a packet-by-packet basis as each of thepackets is received without reassembling the packets. Therefore,processing logic does not have to store the packets for reassembling thepackets. Instead, processing logic may simply store a pointer to keeptrack of the current state in the DFA.

The concept described above may be expanded to signature detection. Asignature is a collection of multiple patterns. To keep track of whichpattern within a signature is being matched, processing logic may use atree structure, where each node within the tree structure corresponds toa pattern and each pattern is represented using a DFA. Alternatively, asingle DFA may represent multiple patterns, an example of which isdiscussed below with reference to FIG. 2B. Processing logic may use apointer to point at the node corresponding to the pattern that iscurrently being matched.

In some embodiments, multiple patterns in a signature are matchedsequentially. That is, once a first pattern is matched, processing logicgoes on to try to match a second pattern. However, processing logic maycontinue looking for the first pattern in the incoming data packetsbecause the first pattern may repeat before the second pattern arrives.In some embodiments, processing logic has to take into consideration ofadditional rules besides matching individual patterns of a signature.For example, a first pattern may have to be at least x bytes away fromthe second pattern, where x is a predetermined number. Alternatively,two patterns of the signature may have to be separated from each otherby y bytes or less, where y is a predetermined number.

FIG. 2B is a state diagram illustrating an exemplary DFA according to analternative embodiment of the invention. In this example, an IPS isprogrammed to detect a pattern of “CAT” and a pattern of “CACHE.” Bothpatterns may be part of a signature. To simplify the illustration, it isassumed in this example that each packet contains only one alphabeticletter. However, it should be appreciated that the concept is applicableto scenarios where a packet contains one or more alphabetic lettersand/or one or more numeric digits.

The DFA 250 includes six states 251-257. Pattern matching begins at theinitial state 251. If a packet received contains a “C,” which is thefirst letter of both “CAT” and “CACHE,” processing logic transitions tothe state 252. If the packet received contains any other alphabet,processing logic remains in the initial state 251. From state 252, ifprocessing logic receives a “C,” then processing logic remains in state252. If processing logic receives an “A,” then processing logictransitions to state 253. If processing logic receives any alphabetother than “A” or “C,” processing logic returns to the initial state251.

From state 253, if processing logic receives a “C,” then processinglogic transitions to state 254 because “C” is the third letter in thepattern “CACHE.” If processing logic receives a “T,” then processinglogic transitions to the final state 257 because the pattern “CAT” ismatched. If processing logic receives any alphabet other than “T” or“C,” processing logic returns to the initial state 251. From state 254,if processing logic receives a “C,” then processing logic transitionsback to state 253. If processing logic receives an “H,” then processinglogic transitions to state 255. If processing logic receives anyalphabet other than “H” or “C,” processing logic returns to the initialstate 251.

From state 255, if processing logic receives a “C,” then processinglogic transitions back to state 252. If processing logic receives an“E,” then processing logic transitions to the final state 256 becausethe pattern matches “CACHE.” If processing logic receives any alphabetother than “E” or “C,” processing logic returns to the initial state251. As discussed above, when processing logic reaches a final state(e.g., state 256 and state 257), processing logic knows that the packetsreceived so far contains at least one of the predetermined patterns.Hence, processing logic may perform the appropriate operations inresponse to receiving the predetermined pattern, such as blocking thepacket of the predetermined pattern last received and issuing an alarmto alert system administrators. Furthermore, to keep track of whichstate of the DFA 250 processing logic is in, processing logic may use alogical pointer to point to the current state of the DFA 250. Furtherdetailed information concerning the above packet scanning techniques canbe found in a co-pending U.S. patent application Ser. No. 11/112,252,entitled “Method and Apparatus for Identifying Data Patterns in a File,”filed Apr. 21, 2005, which has been assigned to a common assignee ofthis application, and which is incorporated by reference herein in itsentirety.

As described above, each DFA state is associated with a data structurefor storing state information for the respective DFA state. Each datastructure is dynamically allocated from a parent state dependent upon aspecific data pattern at the point in time. For example, referring toFIG. 2B, at node or state 253, a next state could be state 254 or state257 dependent upon a specific data pattern. As a result, a DFA datastructure associated with a child node of node 253 may be in a dynamicarray manner or in a linked list manner based on certain rules, whichmay be configured by a network administrator or predetermined policies.

FIG. 3 is a state diagram illustrating an example of DFA states whichmay represent a data pattern. Referring to FIG. 3, in this example, aparent node 301 has two child nodes 302-303, each corresponding to atransition from node 301. Node 302 includes child nodes 304-306, eachcorresponding to a transition from node 302, while node 302 itself is achild node to node 301. Node 303 includes only one child node 307forming a single node chain having nodes 308 and 309.

According to one embodiment, for a given node, if a number oftransitions from this given node to child nodes of this given node isgreater than or equal to a predetermined threshold, the data structuresfor the child nodes are allocated in an array do that the datastructures of the child nodes can be directly accessed from the datastructure of the given node (e.g., parent node). In this configuration,if number of the transitions is relatively large, that means the childnodes or DFA states are frequently accessed from the parent node (e.g.,commonly used data patterns). As a result, it is desirable that the datastructures for all child nodes are maintained and directly accessed fromthe parent node for the purposes of performance, even though thisconfiguration requires more memory (e.g., contiguous or continuous) forthe data structures.

Referring back to FIG. 3, given node 302, it is assumed that the numberof transitions from node 302 to nodes 304-306 is greater than or equalto a predetermined threshold (e.g., 3 in this example). Thus, from thedata structure associated with node 302, data structures for nodes304-306 are allocated in an array (e.g., a continued block of memory)which can be directly and quickly accessed from node 302, as shown inFIG. 4A. In this situation, the benefit of higher performance outweighsthe detriment of requiring a larger memory block. If, however, thenumber of transitions is less than a certain threshold, the datastructures of the child nodes may be allocated in a linked-listconfiguration as shown in FIG. 4B, where each data structure includes afirst reference pointer linked with a data structure of its immediateparent node and a second reference pointer linked with a data structureof one its immediate child node in a chain fashion. In a linked-listconfiguration a parent node has to walk through one child node at a timein order to access to all of its child nodes. In this way, a smallercontinued or contiguous block of memory is needed; however, it may takea longer time to access all the child nodes. Since there are fewer childnodes, memory usage may be reduced and the performance drawback may beminimized.

According to another embodiment, for a given node, if there is only oneimmediate child node (e.g., the whole data sequence is a single childchain where a node has only zero or one child node), a data structure ofthe top parent node of the chain may include most or all necessaryinformation for the child nodes in the chain, optionally in a compressedmanner, to further reduce memory usage without significantlycompromising the performance. In this example as shown in FIG. 3, datastructures for states or nodes 303, and 307-309 may be allocated in acompressed form within the data structure corresponding their rootparent node 301. Examples of pseudo code in C/C++ representing the datastructures are shown in FIGS. 6A-6B.

Furthermore, according to further embodiment, for a given state of asequence of state representing a data sequence, based on a relationshipbetween the given state and its top parent state (e.g., root state), adata structure for the given state may be allocated in a data array orin a linked-list manner. For example, if a given node is within apredetermined distance from its root node, the data structurecorresponding to the given node may be allocated in an array; otherwise,the data structure may be allocated in a linked-list manner. Thedistance threshold may be user configurable and/or specified in the datastructure of the root node.

Referring back to FIG. 3, for example, it is assumed that a datastructure for any node within a three node distance from its root parentnode will be allocated in an array; otherwise the data structure will beallocated in a linked-list manner. Thus, in this example as shown inFIG. 3, data structures for nodes 303 and 307-308 may be allocated in anarray within the data structure for the root node 301, while the datastructure for node 309 may be allocated in a separate data structureaccessible from the data structure corresponding to node 308 via alinked-list manner. Note that the configurations of data structuresdescribed above may be allocated in a mixed or combined manner. Thus,data structures for a particular sequence may be allocated in an arrayin part and in a linked-list manner in part.

FIG. 5A is a flow diagram illustrating a process for data patternanalysis according to one embodiment of the invention. Note that process500 may be performed by processing logic which may include hardware,software, or a combination of both. For example, process 500 may beperformed by a network access device such as network access device 104of FIG. 1. Referring to FIG. 5A, at block 501, for given a current nodeof multiple nodes representing one or more data patterns, where eachnode corresponding to a DFA state, processing logic determines a numberof transitions from the current node to one or more immediate childnodes. If the number of transitions is greater than or equal to apredetermined threshold or alternatively, if a child node is within apredetermined distance from the root node, at block 502, data structuresfor the child nodes are allocated in an array (e.g., continuous block ofmemory) that are directly accessible from the current node. In this way,the data structures of the child nodes can be quickly accessed, but itrequires more memory at block 504. Otherwise, at block 503, each datastructure corresponding to an immediate child node is allocated in alinked-list manner, where the current node has to “walk” throughintermediate nodes in order to reach a node down at the bottom of thelinked-list. In this way, it requires less memory, but the performance(e.g., speed) to access these data structures would be reduced at block504. Other operations may also be performed.

FIG. 5B is a flow diagram illustrating a process for data patternanalysis according to an alternative embodiment of the invention. Notethat process 550 may be performed by processing logic which may includehardware, software, or a combination of both. For example, process 550may be performed by a network access device such as network accessdevice 104 of FIG. 1. Referring to FIG. 5B, at block 551, for given acurrent node of multiple nodes representing one or more data patterns,where each node corresponding to a DFA state, processing logicdetermines whether the child nodes are in a single node chain (e.g.,each node in the chain only has one immediate child node). If so, atblock 552, a single data structure is allocated for the entire chain. Inone embodiment, the single data structure is allocated for the most topparent node of the chain. The data members of the single data structureare used to store all necessary information for each child node in thechain, optionally in a compressed form, which can be directly accessedduring data pattern analysis at block 554. Otherwise, at block 553, thedata structures for the child nodes may be allocated dependent uponother factors such as those shown in FIG. 5A. Other operations may alsobe performed.

FIG. 6A is pseudo code representing a data structure used in a datapattern analysis according to one embodiment. Referring to FIG. 6A, datastructure 600 may be allocated to a parent node of a sequence of datapattern. As described above, data structure 600 representing a parentnode may need to access a data structure of a child node in a formdependent upon a specific configuration of a data pattern. For example,as described above, if the number of transitions from a parent nodeexceeds a predetermined threshold, the data structures of all childnodes are allocated in an array as data member 601 directly accessed bydata structure 600. In this situation, the benefit of higher performancejustifies a larger memory block.

Otherwise, if the number of transitions from a parent node is below apredetermined threshold, the data structures of all child nodes areallocated in a linked-list manner as data member 602 in which a parentnode associated with data structure 600 has to “walk” through each datastructure one at a time. Although it may take longer time to walkthrough, a smaller memory block is needed. Since the number oftransitions is relatively small, the balance of memory usage andperformance is achieved.

In a special situation in which the sequence of data pattern is a singlenode chain, as described above, a single data structure is allocated forall child nodes in a compressed form as data member 603 (with a datastructure example as shown in FIG. 6B). That is, in this situation, onlyone data structure accessed from the parent node is needed to representall child nodes. Since each child node can only have up to twotransitions, either to an immediate parent node or to an immediate childnode, a single data structure is sufficient to cover all necessaryinformation associated with each child node in the chain.

In addition, according to certain embodiments, data structure 600includes data member 604 to store an entry point to a data structure ofa right sibling (e.g., a horizontal sibling as shown in FIG. 3). Datamember 605 is used to store an entry point to each transition state(also referred to as a fail state) when a current state fails to match atarget data. Data member 606 is used to store an entry point of afunction or routine to which processing logic will call when the currentstate matches the target data. Data member 606 may contain additionalinformation about what exactly was matched by the entire sequence, suchas, for example, a pattern ID and/or a function pointer to call when thematch occurs, etc. Data member 607 is used to store the number of childnodes with respect to the current node as a parent node. For example,child count 607 may be used to determine whether certain child nodesshould be allocated in an array or in a linked-list manner.Alternatively, the distance of a particular child node with respect toits root node can be used to determine whether the data structure forthe node should be allocated in an array or in a linked-list manner.Data member 608 is used to store an ASCII content of the current node.

Further, data member 609 is used to indicate whether the data structuresof the child nodes are allocated in an array. If so, data member 601 isvalid; otherwise, data member 602 is valid. Data member 610 is used toindicate whether the childe nodes are in a single node chain; if so,data member 603 will take a precedent. Data structure 600 may furtherinclude certain attributes associated with the current node and/or thesequence of data pattern. For example, data member 611 may be used toindicate whether a particular character should be treated as a casesensitive or insensitive manner. Data member 612 may be used to indicatethat a fail pointer from the current character points to a node with amatch state, in which case, processing logic needs to follow a failpointer and temporarily match something else while the processing logicis walking through the sequence. Note that the format of data structure600 is shown for purposes of illustration only. More or fewer datamembers, as well as other formats, may also be implemented.

FIG. 6B is pseudo code representing a data structure used in a datapattern analysis according to one embodiment. For example, datastructure 650 may be used in a single node data chain (e.g., accessedfrom data structure 600 of FIG. 6A via data member 603). Data structure650 may be allocated as a single data structure to cover all child nodesin the chain, optionally in a compressed form. According to oneembodiment, data member 651 may be used to indicate how many child nodesin the chain. Similar to data member 606 of data structure 600, datamember 652 may include additional information about what exactly wasmatched by the entire sequence, such as, for example, a pattern IDand/or a function pointer to call when the match occurs, etc. Datamember 653 may be used to represent the ASCII content of the chain, suchas, for example, data sequence of “ABCDEFGH”, etc. Data member 654 maybe used to represent certain attributes associated with each characterin the chain, such as those similar to attributes stored in data members611-612 of data structure 600. For example, key[0] may be used to storeattributes associated with character ‘A’ of data member 653. Similar todata member 612 of data structure 600, data member 655 may be used tostore each of the fail states. Also note that the format of datastructure 650 is shown for purposes of illustration only. More or fewerdata members, as well as other formats, may also be utilized.

FIG. 7 is a diagram of a network of computer systems, which may be usedwith an embodiment of the invention. As shown in FIG. 7, a network 700includes a number of client computer systems that are coupled togetherthrough an Internet 722. It will be appreciated that the term “Internet”refers to a network of networks. Such networks may use a variety ofprotocols for exchange of information, such as TCP/IP, ATM, SNA, SDI.The physical connections of the Internet and the protocols andcommunication procedures of the Internet are well known to those in theart. It will be also appreciated that such systems may be implemented inan Intranet within an organization.

Access to the Internet 722 is typically provided by Internet serviceproviders (ISPs), such as the ISP 724, and the ISP 726. Users on clientsystems, such as the client computer systems 702, 704, 718, and 720,generally obtain access to the Internet through Internet serviceproviders, such as ISPs 724 and 726. Access to the Internet mayfacilitate transfer of information (e.g., email, text files, mediafiles, etc.) between two or more digital processing systems, such as theclient computer systems 702, 704, 718, and 720 and/or a Web serversystem 728.

For example, one or more of the client computer systems 702, 704, 718,and 720 and/or the Web server 728 may provide document presentations(e.g., a Web page) to another one or more of the client computer systems702, 704, 718, and 720 and/or Web server 728. For example, in oneembodiment of the invention, one or more client computer systems 702,704, 718, and 720 may request to access a document that may be stored ata remote location, such as the Web server 728. In the case of remotestorage, the data may be transferred as a file (e.g., download) and thendisplayed (e.g., in a window of a browser) after transferring the file.In another embodiment, the document presentation may be stored locallyat the client computer systems 702, 704, 718, and/or 720. In the case oflocal storage, the client system may retrieve and display the documentvia an application, such as a word processing application, withoutrequiring a network connection.

The Web server 728 typically includes at least one computer system tooperate with one or more data communication protocols, such as theprotocols of the World Wide Web and, as such, is typically coupled tothe Internet 722. Optionally, the Web server 728 may be part of an ISPwhich may provide access to the Internet and/or other network(s) forclient computer systems. The client computer systems 702, 704, 718, and720 may each, with appropriate Web browsing software, access data, suchas HTML document (e.g., Web pages), which may be provided by the Webserver 728.

The ISP 724 provides Internet connectivity to the client computer system702 via a modem interface 706, which may be considered as part of theclient computer system 702. The client computer systems 702, 704, 718,and 720 may be a conventional data processing system, such as a desktopcomputer, a “network” computer, a handheld/portable computer, a cellphone with data processing capabilities, a Web TV system, or other typesof digital processing systems (e.g., a personal digital assistant(PDA)).

Similarly, the ISP 726 provides Internet connectivity for the clientcomputer systems 702, 704, 718, and 720. However, as depicted in FIG. 7,such connectivity may vary between various client computer systems, suchas the client computer systems 702, 704, 718, and 720. For example, asshown in FIG. 7, the client computer system 704 is coupled to the ISP726 through a modem interface 708, while the client computer systems 718and 720 are part of a local area network (LAN). The interfaces 706 and708, shown as modems 706 and 708, respectively, may represent an analogmodem, an ISDN modem, a DSL modem, a cable modem, a wireless interface,or other interface for coupling a digital processing system, such as aclient computer system, to another digital processing system.

The client computer systems 718 and 720 are coupled to a LAN bus 712through network interfaces 714 and 716, respectively. The networkinterface 714 and 716 may be an Ethernet-type, asynchronous transfermode (ATM), or other type of network interface. The LAN bus is alsocoupled to a gateway digital processing system 710, which may providefirewall and other Internet-related services for a LAN. The gatewaydigital processing system 710, in turn, is coupled to the ISP 726 toprovide Internet connectivity to the client computer systems 718 and720. The gateway digital processing system 710 may, for example, includea conventional server computer system. Similarly, the Web server 728may, for example, include a conventional server computer system.

In one embodiment, the local area network 712 may be local wirelessnetwork (e.g., a home network) and the gateway 710 may include awireless access point (also referred to as a base station) to one ormore clients 718 and 720 using a variety of wireless networkingprotocols; for example, the IEEE 802.xx protocols including Wi-Fi and/orBluetooth protocols. In a further embodiment, the gateway 710 may accessthe server 728 via dialup network services using a modem.

FIG. 8 is a block diagram of a digital processing system which may beused with one embodiment of the invention. For example, the system 500shown in FIG. 8 may be used as a client computer system such as clients704-705 of FIG. 7. Alternatively, the exemplary system 800 may beimplemented as a network access device 702, etc.

Note, that while FIG. 8 illustrates various components of a computersystem, it is not intended to represent any particular architecture ormanner of interconnecting the components, as such details are notgermane to the present invention. It will also be appreciated thatnetwork computers, handheld computers, cell phones, and other dataprocessing systems which have fewer components or perhaps morecomponents may also be used with the present invention. The computersystem of FIG. 8 may, for example, be an Apple Macintosh computer or anIBM compatible PC.

As shown in FIG. 8, the computer system 800, which is a form of a dataprocessing system, includes a bus 802 which is coupled to amicroprocessor 803 and a ROM 807, a volatile RAM 805, and a non-volatilememory 806. The microprocessor 803, which may be, for example, an Intelprocessor or a PowerPC processor, is coupled to cache memory 804 asshown in the example of FIG. 8. The bus 802 interconnects these variouscomponents together and also interconnects these components 803, 807,805, and 806 to a display controller and display device 808, as well asto input/output (I/O) devices 810, which may be mice, keyboards, modems,network interfaces, printers, and other devices which are well-known inthe art.

Typically, the input/output devices 810 are coupled to the systemthrough input/output controllers 809. The volatile RAM 805 is typicallyimplemented as dynamic RAM (DRAM) which requires power continuously inorder to refresh or maintain the data in the memory. The non-volatilememory 806 is typically a magnetic hard drive, a magnetic optical drive,an optical drive, or a DVD RAM or other type of memory system whichmaintains data even after power is removed from the system. Typically,the non-volatile memory will also be a random access memory, althoughthis is not required.

While FIG. 8 shows that the non-volatile memory is a local devicecoupled directly to the rest of the components in the data processingsystem, it will be appreciated that the present invention may utilize anon-volatile memory which is remote from the system, such as a networkstorage device which is coupled to the data processing system through anetwork interface such as a modem or Ethernet interface. The bus 802 mayinclude one or more buses connected to each other through variousbridges, controllers, and/or adapters, as is well-known in the art. Inone embodiment, the I/O controller 809 includes a USB (Universal SerialBus) adapter for controlling USB peripherals. Alternatively, I/Ocontroller 809 may include an IEEE-1394 adapter, also known as FireWireadapter, for controlling FireWire devices. Other components may also beincluded.

Techniques for data pattern analysis using deterministic finiteautomaton have been described herein. Some portions of the precedingdetailed descriptions have been presented in terms of algorithms andsymbolic representations of operations on data bits within a computermemory. These algorithmic descriptions and representations are the waysused by those skilled in the data processing arts to most effectivelyconvey the substance of their work to others skilled in the art. Analgorithm is here, and generally, conceived to be a self-consistentsequence of operations leading to a desired result. The operations arethose requiring physical manipulations of physical quantities. Usually,though not necessarily, these quantities take the form of electrical ormagnetic signals capable of being stored, transferred, combined,compared, and otherwise manipulated. It has proven convenient at times,principally for reasons of common usage, to refer to these signals asbits, values, elements, symbols, characters, terms, numbers, or thelike.

It should be borne in mind, however, that all of these and similar termsare to be associated with the appropriate physical quantities and aremerely convenient labels applied to these quantities. Unlessspecifically stated otherwise as apparent from the above discussion, itis appreciated that throughout the description, discussions utilizingterms such as “processing” or “computing” or “calculating” or“determining” or “displaying” or the like, refer to the action andprocesses of a computer system, or similar electronic computing device,that manipulates and transforms data represented as physical(electronic) quantities within the computer system's registers andmemories into other data similarly represented as physical quantitieswithin the computer system memories or registers or other suchinformation storage, transmission or display devices.

Embodiments of the present invention also relate to an apparatus forperforming the operations herein. This apparatus may be speciallyconstructed for the required purposes, or it may comprise ageneral-purpose computer selectively activated or reconfigured by acomputer program stored in the computer. Such a computer program may bestored in a computer readable storage medium, such as, but is notlimited to, any type of disk including floppy disks, optical disks,CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), randomaccess memories (RAMs), erasable programmable ROMs (EPROMs),electrically erasable programmable ROMs (EEPROMs), magnetic or opticalcards, or any type of media suitable for storing electronicinstructions, and each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently relatedto any particular computer or other apparatus. Various general-purposesystems may be used with programs in accordance with the teachingsherein, or it may prove convenient to construct more specializedapparatus to perform the required method operations. The requiredstructure for a variety of these systems will appear from thedescription below. In addition, embodiments of the present invention arenot described with reference to any particular programming language. Itwill be appreciated that a variety of programming languages may be usedto implement the teachings of embodiments of the invention as describedherein.

A machine-readable medium may include any mechanism for storing ortransmitting information in a form readable by a machine (e.g., acomputer). For example, a machine-readable medium includes read onlymemory (“ROM”); random access memory (“RAM”); magnetic disk storagemedia; optical storage media; flash memory devices; etc.

In the foregoing specification, embodiments of the invention have beendescribed with reference to specific exemplary embodiments thereof. Itwill be evident that various modifications may be made thereto withoutdeparting from the broader spirit and scope of the invention as setforth in the following claims. The specification and drawings are,accordingly, to be regarded in an illustrative sense rather than arestrictive sense.

What is claimed is:
 1. A method for data pattern analysis of one or morepackets, the method comprising: a processor executing instructionsresiding in memory thereby inspecting the one or more packets for datapatterns; determining a number of transitions from a current node to oneor more subsequent nodes representing one or more sequences of datapatterns, each of the current node and subsequent nodes being associatedwith a deterministic finite automaton (DFA) state; and dynamicallyallocating an array data structure maintained by the current node wheneach of the subsequent nodes includes a single child node.
 2. The methodof claim 1, further comprising the processor storing information foreach child node.
 3. The method of claim 2, wherein the information foreach child node is compressed before it is stored.
 4. The method ofclaim 1, further comprising: the processor dynamically allocating a datastructure for each of the subsequent nodes for storing informationassociated with each of the subsequent nodes in memory, wherein datastructures for the subsequent nodes are dynamically allocated in anarray data structure to optimize performance when the number oftransitions is greater than a predetermined threshold, and wherein datastructures for the subsequent nodes are dynamically allocated in a chaindata structure to optimize memory utilization when the number oftransitions is less than or equal to the predetermined threshold.
 5. Themethod of claim 1, further comprising: the processor identifying a firstpattern; the processor blocking the one or more packets when the firstpattern is detected; and the processor issuing an alarm when the firstpattern is detected.
 6. The method of claim 1, further comprising: theprocessor identifying a plurality of patterns; the processor blockingthe one or more packets when the plurality of patterns are detected; andthe processor issuing an alarm when the plurality of patterns aredetected.
 7. The method of claim 6, wherein: the plurality of patternsform a signature, an earlier pattern precedes a subsequent pattern inthe signature, the processor continues looking for the earlier patternafter the processor has identified the earlier pattern while theprocessor is looking for the subsequent pattern.
 8. The method of claim6, wherein: the plurality of patterns form a signature, an earlierpattern precedes a subsequent pattern in the signature, and the earlierpattern must be separated from the subsequent pattern by a predeterminednumber of bytes or more for the subsequent pattern to be identified as aportion of the signature.
 9. The method of claim 6, wherein: theplurality of patterns form a signature, an earlier pattern precedes asubsequent pattern in the signature, and the earlier pattern must beseparated from the subsequent pattern by a predetermined number of bytesor less for the subsequent pattern to be identified as a portion of thesignature.
 10. A non-transitory computer storage medium embodied thereona program executable to perform a method for data pattern analysis ofone or more packets, the method comprising: a processor executinginstructions residing in memory thereby inspecting the one or morepackets for data patterns; determining a number of transitions from acurrent node to one or more subsequent nodes representing one or moresequences of data patterns, each of the current node and subsequentnodes being associated with a deterministic finite automaton (DFA)state; and dynamically allocating an array data structure maintained bythe current node when each of the subsequent nodes includes a singlechild node.
 11. The non-transitory computer readable storage mediummethod of claim 10, further comprising the processor storing informationfor each child node.
 12. The non-transitory computer readable storagemedium method of claim 11, wherein the information for each child nodeis compressed before it is stored.
 13. The non-transitory computerreadable storage medium method of claim 10, further comprising: theprocessor dynamically allocating a data structure for each of thesubsequent nodes for storing information associated with each of thesubsequent nodes in memory, wherein data structures for the subsequentnodes are dynamically allocated in an array data structure to optimizeperformance when the number of transitions is greater than apredetermined threshold, and wherein data structures for the subsequentnodes are dynamically allocated in a chain data structure to optimizememory utilization when the number of transitions is less than or equalto the predetermined threshold.
 14. The non-transitory computer readablestorage medium method of claim 10, further comprising: the processoridentifying a first pattern; the processor blocking the one or morepackets when the first pattern is detected; and the processor issuing analarm when the first pattern is detected.
 15. The non-transitorycomputer readable storage medium method of claim 10, further comprising:the processor identifying a plurality of patterns; the processorblocking the one or more packets when the plurality of patterns aredetected; and the processor issuing an alarm when the plurality ofpatterns are detected.
 16. The non-transitory computer readable storagemedium method of claim 15, wherein: the plurality of patterns form asignature, an earlier pattern precedes a subsequent pattern in thesignature, the processor continues looking for the earlier pattern afterthe processor has identified the earlier pattern while the processor islooking for the subsequent pattern.
 17. The non-transitory computerreadable storage medium method of claim 15, wherein: the plurality ofpatterns form a signature, an earlier pattern precedes a subsequentpattern in the signature, and the earlier pattern must be separated fromthe subsequent pattern by a predetermined number of bytes or more forthe subsequent pattern to be identified as a portion of the signature.18. The non-transitory computer readable storage medium method of claim15, wherein: the plurality of patterns form a signature, an earlierpattern precedes a subsequent pattern in the signature, and the earlierpattern must be separated from the subsequent pattern by a predeterminednumber of bytes or less for the subsequent pattern to be identified as aportion of the signature.